Post-Synthesis STA Analysis: Performs setup analysis on different path groups.įloorplanning – Goal is to plan the silicon area and create a robust power distribution network (PDN) to power each of the individual components of the synthesized netlist. Each standard cell comes with SPICE, HDL, liberty, layout (detailed and abstract) files used by different tools at different stages in the RTL2GDS flow. This width is an integer multiple of the SITE size or the PR boundary. Standard Cells – Standard cells are fixed height and a multiple of unit size width. Technology Mapping – Consists of mapping the post-optimized GTECH netlist to standard cells described in the PDK GTECH Mapping – Consists of mapping the HDL netlist to generic gates what are used to perform logical optimization based on AIGERs and other topologies created from the generic mapped netlist. The synthesis process is normally performed in two major steps:

Logic Synthesis – Logic synthesis uses the RTL netlist to perform HDL technology mapping. RTL Verification - Behavioral verification of designĭFT Insertion - Design-for-Test Circuit Insertion This method bridges the gap between C and HDL allowing HDL design to be performed Behavioral Modeling – Allows the microarchitecture modeling to be performed with behavior-based modeling in HDL. It provides an abstraction of the digital circuit using:ī. RTL Design – Stands for Register Transfer Level. One of two design methods may be employed while creating the HDL of a microarchitecture:Ī. HDL modeling is normally performed using either Verilog or VHDL.

EDA tools will use the HDL to perform mapping of higher-level components to the transistor level needed for physical implementation. RTL Design/Behavioral Modeling – RTL design and behavioral modeling are performed with a hardware description language (HDL). The VLSI engineer will be required to design a circuit that meets these specification at a microarchitecture modeling level. The flow can be broken down into 11 steps:Īrchitectural Design – A system engineer will provide the VLSI engineer with specifications for the system that are determined through physical constraints. The details of the flow may change depending on ECO’s, IP requirements, DFT insertion, and SDC constraints, however the base concepts still remain. This project give a detailed view in generating a final layout to print photomasks used in the fabrication of a behavioral RTL (Register-Transfer Level) of an 8-bit parity generator, using SkyWater 130 nm PDKįrom conception to product, the ASIC design flow is an iterative process that is not static for every design. In this project 8-bit odd and even parity generator is implemented using google skywater130 PDK (Process Design Kit).

Design of 8 bit Parity generator using sky130nm technology

8 bit even parity generator vhdl code